The present invention relates to a memory device and more particularly to a well bias circuit and a method of protecting the well bias circuit when a power supply is turned on after the power supply is abnormally turned off.
A nonvolatile semiconductor memory storage device maintains stored data even when the supply of power is stopped. Accordingly, the nonvolatile memory device is widely employed (e.g., in a computer, a memory card, etc).
A NAND flash memory device has higher density compared with a NOR flash memory device, and thus the NAND flash memory device is widely employed in a high integration flash memory device.
A memory cell array of the NAND flash memory device has a plurality of memory cells and a string where two select transistors, i.e. source select transistor (SST) and ground select transistor (GST) are connected in series. Here, the select transistors are connected to a bit line and a source line.
The select transistor (GST) performs a switching operation for connecting to a reference common line.
The select transistor (SST) switches a connection between the memory cell and the bit line for data input/output.
To read certain information from the memory cell, the NAND flash memory device applies a voltage of about 4.5V to gates of the select transistors SST and GLT, thereby turning on the select transistors SST and GLT. Then, in this condition, the NAND flash memory device applies a voltage of 0V to a word line of a selected memory cell, and applies a voltage of 4.5V to a word line of a memory cell which is not selected. As a result, the word line corresponding to the selected memory cell is activated. Accordingly, the NAND flash memory device may read information stored in the selected memory cell without effect of peripheral memory cells.
Additionally, to erase data of the memory cell in the memory device, a high voltage is applied to a substrate, i.e. well, and then data of a programmed memory cell is erased.
Hence, a circuit for applying a well bias has a first path through which a well bias having a high voltage is applied, and a second path through which the voltage of the well is discharged, wherein the first path is different from the second path. Further, the circuit includes a well bias circuit for controlling the well bias so that the well bias has always a ground voltage, e.g., 0V in case that an erase operation is not performed.
FIG. 1 is a view illustrating a common well bias circuit in the NAND flash memory.
In FIG. 1, the well bias circuit includes a well voltage supplying circuit 10, a well to ground circuit 20, a well discharging circuit 30 and a controller 40. Here, the well voltage supplying circuit 10 supplies a high voltage to a well so as to erase data of a memory cell (not shown), and the well to ground circuit 20 controls the well bias so that the well bias has a ground voltage, e.g., 0V when an erasing operation is not performed. In addition, the well discharging circuit 30 provides a discharge path so that the high voltage supplied to the well is discharged after the erasing operation, and the controller 40 outputs a controlling signal for controlling the operation of the well to ground circuit 20 and the well discharging circuit 30.
The well voltage supplying circuit 10 has a first snapback transistor Sb1 connected between an input terminal having the high voltage VERASE and a node 1. Here, a switching controlling signal SW_HV is transmitted to a gate of the first snapback transistor Sb1, and the node 1 is connected to the well in the NAND flash memory. Additionally, the first snapback transistor Sb1 has characteristics for withstanding a high voltage, and thus other transistors having characteristics for withstanding the high voltage may be substituted for the first snapback transistor Sb1.
The well to ground circuit 20 includes a second inverter IN2, a third inverter IN3, and an N-MOS transistor N1.
The second and third inverters IN2, IN3 are connected in series between a first inverter IN1 (for inverting a well to ground inverting signal WELLTOGND_N) and a node 2.
The N-MOS transistor N1 is connected between the node 1 and a ground GND. Here, a gate of the N-MOS transistor N1 is connected to the node 2. On the other hand, the N-MOS transistor N1 should be sized large so that the well bias has a stable 0V because the well has a high capacitance. In this case, a common N-MOS transistor is employed as the N-MOS transistor N1.
The well discharging circuit 30 includes a fourth inverter IN4, a fifth inverter IN5, and a second snapback transistor Sb2.
The fourth and fifth inverters IN4, IN5 are connected in series between a discharge controlling signal DISCH terminal of the controller 40 and a node 3.
The second snapback transistor Sb2 is connected between the node 1 and the ground GND. Here, a gate of the second snapback transistor Sb2 is connected to the node 3.
The controller 40 outputs the discharge controlling signal DISCH for discharging the high voltage applied to the well in order to erase data in the memory, and the well to ground inverting signal WELLTOGND_N for controlling the well bias so that the well bias has 0V.
The well to ground inverting signal WELLTOGND_N is inverted by the first inverter IN1, and so a well to ground controlling signal WELLTOGND is generated. Subsequently, the well to ground controlling signal WELLTOGND is inputted into the well to ground circuit 20 through the second and third inverters IN2, IN3.
To erase data in the memory, the controller 40 outputs the well to ground inverting signal WELLTOGND_N having high level, and then the outputted well to ground inverting signal WELLTOGND_N is changed into the well to ground controlling signal WELLTOGND having low level through the first inverter IN1.
Subsequently, the well to ground controlling signal WELLTOGND is inputted to the well to ground circuit 20 via the second and third inverters IN2, IN3. As a result, the first N-MOS transistor N1 is turned off in accordance with the well to ground controlling signal WELLTOGND having low level. In addition, the switching controlling signal SW_HV is inputted to the gate of the first snapback transistor Sb1. In this case, the switching controlling signal SW_HV is provided from a high voltage switch (not shown) so as to apply the high voltage for erase.
In case that the switching controlling signal SW_HV has high level, the first snapback transistor Sb1 is turned on, and so the high voltage VERASE is applied to the well through path a. Here, the high voltage VERASE has different magnitudes in accordance with the characteristics of the memory, e.g. about 20V.
Level of the switching controlling signal SW_HV is converted into low level after data in the memory cell is erased by the high voltage VERSE applied to the well, and so the first snapback transistor Sb1 of the well voltage supplying circuit 10 is turned off. Additionally, the controller 40 outputs the discharge controlling signal DISCH having high level so as to discharge the high voltage VERASE applied to the well.
The second snapback transistor Sb2 of the well discharging circuit 30 is turned on by the discharge controlling signal DISCH, and so discharge path b is formed to discharge the high voltage of the well connected to node 1.
The well bias circuit may have a problem when a power supply is turned on after being turned off during an erase operation. In this case, the controller 40 outputs the well to ground inverting signal WELLTOGND_N having low level when the power supply has on status. Accordingly, the well to ground controlling signal WELLTOGND has high level by the first inverter IN1, and so the N-MOS transistor N1 is turned on. As a result, the well bias has 0V.
However, since the power supply is turned off during the erase operation, the high voltage VERASE is already applied to the well, and so the N-MOS transistor N1 may be damaged by the high voltage VERSE provided from the well.
Hereinafter, operation simulation of the well bias circuit will be described with reference to FIG. 2.
FIG. 2 is a view illustrating simulation result in accordance with discharging the well voltage in FIG. 1.
Referring to FIG. 2, a well to ground controlling signal SWDW_WELLTOGND of the controller 40 maintains high level during a power has on condition in accordance with a power on inverting signal PWRONEN_N. Accordingly, in case that the power supply is turned off during erase operation, the high voltage is provided from the well to the N-MOS transistor N1 of the well to ground circuit 20, and so the N-MOS transistor N1 may be damaged.